Conventionally, a class AB output stage is used to drive big MOS transistors in power applications. As shown in FIG. 1, a typical class AB output stage 10 includes a driver 12 to provide two drive signals UH and UL, and two bias voltage sources 16 and 18 to provide bias voltages VOS1 and VOS2, respectively, which are used to level shift the drive signals UH and UL to produce the gate voltages for driving a pair of high side transistor MP and low side transistor MN serially connected between a power supply Vcc and a ground terminal GND, in order to supply a current for a load RL connected to an output LX. Typically, the driver 12 uses an operational amplifier 14 to produce the drive signals UH and UL according to an input signal Vin and a feedback signal from the output LX. The bias voltages VOS1 and VOS2 are the key to the quiescent current control and total harmonic distortion (THD) of this circuit. The quiescent current refers to the current consumed by this circuit from the power supply Vcc under loadless condition, i.e., without the load RL. For driving a resistive load RL, there are many factors, including crossover distortion, power consumption through the big MOS paths and loop stability, must be taken into consideration at the same time for the design of the class AB output stage 10. The target of the design region is shown in FIG. 2, in which the X-axis represents the bias voltages VOS1 and VOS2, the left Y-axis represents the THD, the right Y-axis represents the quiescent current IQ, the curve 20 represents the relationship between the THD and the bias voltages VOS1 and VOS2, and the curve 22 represents the relationship between the quiescent current IQ and the bias voltages VOS1 and VOS2. As shown by the curves 20 and 22, as the bias voltages VOS1 and VOS2 increase, the THD decreases whereas the quiescent current IQ increases; contrarily, for smaller quiescent current IQ, the THD is greater. A dash circle 24 marks the ideal design region of the bias voltages VOS1 and VOS2, where it may have lower quiescent current IQ and better THD performance at the same time. However, this design region 24 is quite sensitive to process variation and as a result, the bias voltages VOS1 and VOS2 may deviate from the design region 24 due to the process variation in real applications. Therefore, solutions are needed for the bias voltages VOS1 and VOS2 to return to the target design region 24 against process variation.
U.S. Pat. No. 5,481,213 to Johnson has proposed a cross-conduction prevention circuit for power amplifier output stage, which may get a best THD performance and a reasonable quiescent current if the width/length size of some MOS transistors in a fill-in circuit is well designed. However, this solution requires adding the fill-in circuit and an extra control circuit into the output stage and thus results in a relatively complicated structure. Moreover, the fill-in circuit and the extra control circuit may be interfered by each other, thus leading to system instability. On the other hand, the bias point of this output stage is not programmable and thus cannot be adjusted to reduce or remove the error resulted from process variation.
Therefore, a simpler class AB output stage with programmable bias point control is desired.